For systems having a plurality of shared resources such as memories, I/O devices, buffers, etc. . . . , it is of interest to provide a concurrent access to said shared resources, and preferably in a transparent manner for the users or multiprocessors, versus the physical system configuration.
A shared memory computer apparatus providing concurrent access to a plurality of users, has been described in European patent 0023213-B1.
The problem addressed therein consists in providing conflict-free access to shared memory modules, without loss of performance when the number of accesses and the number of memory modules are increased. To reach this result, means are provided, in the form of a random address generator connected for receiving the access requests and for translating addresses received with said request into randomly distributed addresses with respect to the memory units.
However, this prior art system does not provide a sufficient transparency to the users versus the actual, or physical addresses of information within the memory modules, since said prior art system only uses logical addressing for address randomization purposes. Besides, the commands used by the processor to accede to the shared memory are conventional Write, Read or Test commands, and the memory record are not dynamically expendable.